This invention relates to the field of methods for processing semiconductor materials, and in particular to methods for overcoming alignment offset problems in the fabrication of a semiconductor which can exist between an interconnect layer and a contact layer or between an interconnect layer and a via layer, which thereby provide a simplified hole inconnect process.
Many semiconductor processes employ fabrication steps in which aligned openings are formed in adjacent interconnect and contact layers or in adjacent interconnect and via layers. The interconnect layer is typically a metal layer and the contact layer or via layer is typically an insulating/dielectric layer. However, a significant problem exists in that instead of being in substantial alignment with each other, the opening in the interconnect layers can easily become offset during processing unless substantial steps are undertaken to avoid such misalignment.
In order to overcome the above-described offset alignment problem, a number of additional incremental steps have been introduced to augment prior art semiconductor 100 fabrication schemes. In known commercial processes, the formation of a contact or via hole pattern requires a number of method steps. For example, as shown in FIG. 1A, an insulating/dielectric layer 112 is first deposited onto a substrate layer 110. Then, a series of resist photomasking process must be employed.
As shown in FIG. 1B, a resist layer 114 is, for instance, spun onto an contact insulating/dielectric layer 112 which was previously disposed onto an underlying silicon wafer substrate 110. Then, as seen in FIG. 1C, the resist 114 is exposed using UV light and then developed to form a three dimension relief image in a predetermined pattern including openings 116 in the resist layer down to the insulating/dielectric layer 112. Next, the insulating/dielectric layer 112 is etched through the contact opening 116 in the resist layer 114 down to the silicon substrate 110, employing conventional etching techniques (see FIG. 1D), followed by removal of the resist layer 114 from the surface of the insulating/dielectric layer 112 (see FIG. 1E).
In FIG. 1F, an interconnect layer 120, which is typically formed of a metallic material, is then deposited into the contact opening 116 and onto the patterned insulating/dielectric layer 112. This necessitates employing another resist photomasking sequence which includes the processing steps needed to align the openings in the subsequently etched interconnect pattern and the openings in the previously formed insulating/dielectric layer hole pattern (see FIG. 1G). Once the resist layer 114 is spun on, and the requisite predetermined pattern formed therein (see FIG. 1H), the interconnect layer 120 is etched through the openings 118 in the resist layer 114 down to the insulating/dielectric substrate 112, employing conventional etching techniques (see FIG. 1I). After etching of the interconnect layer 120 is completed, the interconnect pattern remaining on the underlying contact film, creates a topography needing special subsequent planarizing techniques.
Disadvantages of the above-described known methods are the increased number of photomasking and etch processing steps, the additional alignment tolerances needed between interconnect and hole layers, the increased step height between interconnect vs. non-interconnect areas, and the need for additional post-interconnect pattern contact planarization processing steps.
There is thus a need exists for simplifying the above-described processes to reduce the cost of semiconductor wafer manufacture while providing a process which eliminates alignment offset problems between an interconnect layer and a contact layer or between an interconnect layer and a via layer.